Consequently, the current creation is not meant to be restricted to the embodiments demonstrated herein but will be to be accorded the widest scope per the ideas and novel options disclosed herein.
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A small distinction as a consequence of ordinary environmental modifications including temperature might be inside of a predetermined detection threshold. A substantial distinction in violations as a result of tampering (frequency and/or voltage) are going to be beyond the predetermined detection threshold.
33. The equipment for detecting voltage tampering as outlined in claim 30, wherein the usually means for evaluating decides no matter whether the volume of ones in the plurality of delayed monotone alerts differs from a drinking water degree variety by greater than a predetermined threshold.
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Exactly what is claimed is: 1. A method for detecting clock tampering, comprising: providing a plurality of resettable hold off line segments, whereby resettable hold off line segments between a resettable delay line segment associated with a minimum amount hold off time and also a resettable hold off line phase affiliated with a highest delay time are Each and every connected with discretely expanding hold off periods;
fifteen. An apparatus for detecting clock tampering, comprising: a circuit that provides a monotone sign in the course of a clock Examine time frame associated with a clock;
The second clock Consider time period handles a distinct time than the initial clock Examine time frame, as could possibly be enforced by an inverter 730. The second plurality of resettable hold off line segments Every hold off the 2nd monotone signal to create a respective next plurality of delayed monotone signals. Resettable delay line segments between a resettable hold off line phase affiliated with a bare minimum hold off time and a resettable delay line phase related to a greatest hold off time are Every related to discretely growing hold off moments. The Assess circuit is triggered because of the clock (e.g., EVAL) and uses the primary plurality of delayed monotone signals or the second plurality of delayed monotone alerts to detect a clock fault. A multiplexer 760 may possibly find which of the initial or next plurality of delayed monotone signals are Energetic to be furnished towards the Consider circuit.
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a plurality of resettable delay line segments that hold off the monotone sign to crank out a respective plurality of delayed monotone signals Every single owning both a one particular or simply a zero logic value, wherein resettable delay line segments in between a resettable hold off line segment linked to a minimum hold off time as well as a resettable hold off line phase linked to a maximum hold off time are Every single connected to discretely increasing delay situations; and
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Yet another facet of the invention may perhaps reside in an apparatus for detecting clock tampering, comprising: implies 250 for delivering a monotone sign 220 through a clock Appraise time period 310 connected to a clock CLK; usually means 210 for delaying the monotone signal utilizing a plurality more info of resettable delay line segments to deliver a respective plurality of delayed monotone indicators 230 possessing discretely rising delay moments amongst a minimal delay time along with a most delay time; and indicates 240 for utilizing the clock CLK to cause an Examine circuit 240 that employs the plurality of delayed monotone indicators to detect a clock fault.
In other a lot more detailed areas of the invention, each in the plurality of delayed monotone signals may be either a one or even a zero. The Assess circuit may perhaps determine no matter if the amount of types within the plurality of delayed monotone alerts differs from a water degree selection by over a predetermined threshold.